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Barua, Rajeev

Professor
1431 A.V. Williams Building
Phone: 
301.405.8137

Research Interests 

Dr. Barua's research interests are in the areas of compilers, embedded systems, and computer architecture. Recent work has tackled the problem of compiler approaches to reliable software in embedded systems, memory allocation for embedded systems, and compiling to VLIW processors. Earlier work has targeted memory disambiguation technologies, instruction scheduling, ASIP customization, silicon compilation, instruction prefetching, partitioning of memory on multiprocessors, and a study of memory latency and bandwidth characteristics on multiprocessors.

Video 

Background 

Dr. Rajeev Barua is an Associate Professor of Electrical and Computer Engineering at the University of Maryland and an affiliate faculty member in the Institute for Systems Research and the Department of Computer Science department. He received his Ph.D in Computer Science and Electrical Engineering from the Massachusetts Institute of Technology in 2000.

Dr. Barua is a recipient of the NSF CAREER award in 2002, and of the UMD George Corcoran Award for teaching excellence in 2003. He was a finalist for the Inventor of the Year Award in 2005 given by the Office of Technology Commercialization at the University of Maryland. He received the President of India Gold Medal for graduating from the Indian Institute of Technology in 1992 with the highest GPA in the university that year.

He served as Workshops Chair for the ACM Conference on Compilers, Architecture, & Synthesis for Embedded Systems (CASES) in 2004. He also served as Program Co-Chair for the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), also in 2004. Over the years, he have served on several NSF panels and on the program committees of several leading academic conferences.

 

Honors and Awards 

Young Faculty Award
NSF CAREER award for "Synthesis-Assistance and Compilation Software for Embedded Systems", 2001

University of Maryland
George Corcoran Award for teaching excellence, 2003


Related News 

Vishkin, Barua and Ghanim Introduce ICE to Eliminate Programmer’s Multi-Threading – A Productivity-Buster in Parallel Computing
Intermediate Concurrent Execution (ICE) enables tightly-synchronous threading-free programming for multi-threaded execution.October 24, 2017

TEDCO Invests $1M into Innovative Companies Including Rajeev Barua’s Startup SecondWrite LLC
SecondWrite LLC has received TEDCO funding from the state of Maryland for an amount of $100,000.July 27, 2017

Danny Kim, MWC/ARCS Lockheed Martin Scholar, will continue malware mitigation technology research
Danny receives ARCS Scholarship for third consecutive year.May 24, 2017

Matthew Gilboy wins Dean's Masters Student Research Award
Gilboy wins for his thesis, “Fighting Evasive Malware With Dvasion.”May 11, 2016

Rajeev Barua promoted to full professor
Barua is known for his work in compilers, embedded systems and computer architecture.April 17, 2015

ECE Names 2012-2013 Distinguished Dissertation Fellows
Anand, Fan, Guan, and Xie recognized for outstanding research.April 4, 2013

Alex Tzannes wins ACM Student Research Competition
Award presented for paper on improving run-time scheduling.October 24, 2011

Grad student Timothy Creech receives Space Technology Research Fellowship
Student of Rajeev Barua is one of six from the Clark School to win NASA fellowship.August 2, 2011

Intelligent Automation, Inc. to sponsor colloquia series
IAI president and ISR alumnus Vikram Manikonda announces generous support.January 11, 2011

Barua wins NSF grant for new binary rewriter
The rewriter will allow any binary code to be rewritten and improved.August 31, 2009

Barua, Cleaveland, Sussman win DARPA funding for AESOP project
UMD will collaborate with Princeton, BAE Systems to compile serial programs into parallel programs.July 29, 2009

Rajeev Barua is Principal Investigator for NSF Compiler Optimizations Grant
Uzi Vishkin is co-PI for three-year, $400,000 award.September 3, 2008

Barua, Udayakumaran awarded patent for memory allocation
Prof. Barua and his former student were awarded a patent for a new dynamic memory allocation methodology.June 6, 2008

Barua awarded NSF grant for memory management as a run-time service
Research will develop a scratch pad memory allocation strategy implemented inside a binary rewriter.August 21, 2007

ECE Professor Introduces New "Desktop Supercomputing"
Uzi Vishkin's group develops first easy-to-program parallel processing supercomputer prototype.June 24, 2007

Simulator of the Explicit Multi-Threading (XMT) Computer Architecture and Software Tools for Programming It (ISR IP)
This IP is available to license.June 24, 2007

Binary Rewriting Without Relocation Information (ISR IP)
This IP is available to license.June 23, 2007

Automatic Parallelization Using Binary Rewriting (ISR IP)
This IP is available to license.June 23, 2007

A Dynamic Memory Allocator for Embedded Systems with Scratch-Pad Memory (ISR IP)
This IP is available to license.June 21, 2007

ISR alum Haga joins faculty at National Sun Yat-Sen University, Taiwan
Former student of Rajeev Barua will continue research in compiler techniques for embedded processors.February 28, 2007

ECE Faculty Promotions Announced
Two promoted to professor and four promoted to associate professor.April 27, 2006

Shapiro, Barua, Ulukus and Wu receive tenure
Four ISR faculty promoted to associate professor rankMarch 16, 2006

Ephremides is PI for NSF MRI grant on wireless sensor networks
Project will develop experimental prototypes of intelligent embedded systemsSeptember 3, 2005

ISR faculty win two Invention of the Year awards
Faculty recognized in information science and physical science categoriesApril 2, 2005

Barua receives TEDCO "significant commercial potential" award
ISR faculty member to study “A Dynamic Memory Allocator for Embedded Systems with Scratch-Pad Memory.”September 4, 2004

Barua is co-principal investigator for five-year, $700K NSF grant
Research will investigate parallel random-access model (PRAM)-on-chip.September 2, 2003