The Institute for Systems Research
Maryland Energy Innovation Institute
Dr. Rajeev Barua is a Professor of Electrical and Computer Engineering at the University of Maryland and an affiliate faculty member in the Institute for Systems Research and the Department of Computer Science. He received his Ph.D in Computer Science and Electrical Engineering from the Massachusetts Institute of Technology in 2000.
Dr. Barua is a recipient of the NSF CAREER award in 2002, and of the UMD George Corcoran Award for teaching excellence in 2003. He was a finalist for the Inventor of the Year Award in 2005 given by the Office of Technology Commercialization at the University of Maryland. He received the President of India Gold Medal for graduating from the Indian Institute of Technology in 1992 with the highest GPA in the university that year.
He served as Workshops Chair for the ACM Conference on Compilers, Architecture, & Synthesis for Embedded Systems (CASES) in 2004. He also served as Program Co-Chair for the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), also in 2004. Over the years, he has served on several NSF panels and on the program committees of several leading academic conferences.
Honors and awards
• NSF CAREER Award (2002)
• George Corcoran Award (2003)
• Finalist, Inventor of the Year Award, University of Maryland (3 finalists among 35 invention submissions) (2004)
Dr. Barua's research interests are in the areas of compilers, embedded systems, and computer architecture. Recent work has tackled the problem of compiler approaches to reliable software in embedded systems, memory allocation for embedded systems, and compiling to VLIW processors. Earlier work has targeted memory disambiguation technologies, instruction scheduling, ASIP customization, silicon compilation, instruction prefetching, partitioning of memory on multiprocessors, and a study of memory latency and bandwidth characteristics on multiprocessors.
- NSF CSR: Easy PRAM-Based High-Performance Parallel Programming with Immediate Concurrent Execution (ICE)
- Binary Rewriting without Relocation Information
- Adaptive Environment for Supercompiling with Optimized Parallelism (AESOP)
- NSF CSR-PSCE,SM: Compiler-Directed System Optimization of a Highly-Parallel Fine-Grained Chip Multiprocessor
- NSF CSR-EHS: Memory management as a run-time service