An integrator-multiplier-integrator circuit scheme usable in transverse fers, a transverse filter employing such a circuit, and a method for using each. The multiplier-integrator-multiplier has a capacitatively loaded integrating amplifier fed by a transistor. The current through the transistor, and hence the time it takes to charge the integrating capacitor, depends largely on the bias of the transistor, not the size of the capacitor, permitting one to set and control integration time by setting the transistor's parameters, and controlling its bias, effectively controlling integration time by us of only one semiconductor device. An additional circuit for auto-zeroing (i.e. canceling quiescent offset) increases adaptivity of the circuit. Preferably the phase of inputs to the first multiplier is made selectably variable to minimize phase difference at the multiplier, thus increasing circuit stability.
U.S. Patent and Trademark Office DescriptionPTO
Eric Justh, Francis Kub