NSF: Optimization Schemes for Large Scale Digital Circuits in Presence of Fabrication Randomness

Reduction in fabrication dimensions has resulted in significant increase in the randomness associated with the fabricated parameters of large scale digital circuits. This has begun to severely impact the manufacturing yield and therefore the profitability of the semiconductor industry. In this research the investigators are focusing on developing formal optimization schemes for synthesizing large scale digital circuits while proactively considering randomness induced yield loss as an optimization criteria.

Optimization Schemes for Large Scale Digital Circuits in Presence of Fabrication Randomness is a four-year, $150K grant.