IAI Colloquia Series at ISR: Rajeev Barua, "AESOP Parallelizing Compiler"
Wednesday, May 11, 2011
1146 A.V. Williams Building
301 405 6615
Intelligent Automation, Inc. Colloquia Series
@ The Institute for Systems Research
AESOP: A parallelizing compiler for high performance computing
Institute for Systems Research
Department of Electrical and Computer Engineering
University of Maryland
College Park, Md.
| View the video from this seminar |
Generating good parallel code automatically from serial programs remains one of the grand challenges of computing in the multi-core era. Even when parallel code is generated, the increasing complexity of modern computing systems makes it difficult to achieve even a reasonable fraction of a systems available performance. Unfortunately, the level of sophistication and expertise required to develop and tune a program is growing along with the complexity of the underlying systems.
We are developing the AESOP compiler, which is a computationally efficient compiler that incorporates learning and reasoning methods to drive compiler optimizations for a broad spectrum of computing system configurations. It incorporates state-of-the-art technologies to automatically parallelize serial code. It also learns about the characteristics of the underlying hardware both statically and dynamically to drive optimization selection. Results show the effectiveness of proposed approach in parallelizing programs in an architecture-aware manner.
Dr. Rajeev Barua is an Associate Professor of Electrical and Computer Engineering at the University of Maryland. He received his Ph.D in Computer Science and Electrical Engineering from the Massachusetts Institute of Technology in 2000. Dr. Barua is a recipient of the NSF CAREER award in 2002, and of the UMD George Corcoran Award for teaching excellence in 2003. He was a finalist for the Inventor of the Year Award in 2005 given by the Office of Technology Commercialization at the University of Maryland. Dr. Barua's research interests are in the areas of compilers, automatic parallelization, embedded systems, and binary rewriting.