Rajeev Barua is Principal Investigator for NSF Compiler Optimizations GrantAssociate Professor Rajeev Barua (ECE/ISR) is the principal investigator and Professor Uzi Vishkin (ECE/UMIACS) is co-principal investigator of a three-year, $400,000 National Science Foundation grant, Compiler-Directed System Optimization of a Highly-Parallel Fine-Grained Chip Multiprocessor.
This project will study compiler optimizations for the XMT multiprocessor designed in the Clark School of Engineering at the University of Maryland.
Accelerating single programs on multicore processors is a top challenge in computer systems design. Only computer programs using regular dense-matrix codes run faster on existing parallel systems. Unfortunately, most programs use "non-regular" code.
Some non-regular codes have little parallelism beyond instruction level parallelism (ILP) and cannot run faster on multicores. But for other non-regular code, parallelism is present but not exploitable.
Vishkin has received international attention for his related research, which included the development of a desktop supercomputing prototype capable of speeds 100 times faster than current desktops, representing a paradigm for the next generation of computers. In future devices, the XMT technology could include 1,000 processors on a chip the size of a finger nail.
This grant supports a project to develop new compiler technologies for XMT to achieve scalable performance in the face of architecture decisions made for scalability. The researchers will study better compiler techniques to achieve scalable performance for UMA architectures such as XMT, including better task schedulers using global queues rather than work stealing; improved pre-fetching tailored for XMT's unique memory hierarchy; and using scalable non-cache-coherent Scratch-Pad Memory local to each XMT processor to reduce the need to go to expensive remote memory.
Outcomes of the research will include developing compiler technologies that will reduce the research risk of XMT to the point where industry is willing to commercialize the technology; delivering scalable speedups for hard-to-parallelize applications; demonstrating robust performance across large classes of serial, regular parallel, and non-regular parallel programs; and demonstrating a serious contender for a future universal desktop architecture.
The grant is being administered by NSF's Computer Systems Research (CSR) program in the CISE directorate.
Published September 3, 2008