ISR/ECE faculty organizing, moderating panel at CADforAssurance

Registration is required to view the panel. Register here.

Panel 5: "Hardware Assurance for AI: Friend or Foe?"

Moderated by ISR Director Ankur Srivastava and Swarup Bhunia of the University of Florida.

Panelists

Mike Borza, Synopsys
Vivian Kammler, Sandia National Lab
Brian Knight, Microsoft
Len Orlando, Air Force Research Lab (AFRL)
Sam Weber, Office of Naval Research (ONR)

Assurance of electronic hardware against diverse security and trust issues has become a complex, challenging problem. On one hand, explosion of design complexity demand a highly sophisticated design and verification process. On the other, hardware lifecycle for both ASIC and COTS (e.g., FPGA, microcontroller, etc.) components, increasingly involve multitude of trust issues, requiring new thinking in system design and verification that can address the underlying lack of trust. AI techniques have shown great promises in mitigating these issues from rapid exploration of viable attack space to detection of anomalous design artifacts. While
the power of AI/ML is poised to make transformative impact on hardware assurance, the research community has also identified assurance issues with AI/ML hardware themselves. In particular, their vulnerability against malicious manipulations, information leakage, and other attacks have created major concerns. This panel will examine the crucial challenge of hardware assurance in the modern supply chain ecosystem, evolving role of AI/ML in hardware assurance, and discuss their interdependence/conflicts.

Published August 11, 2022