Barua, Rajeev
The Institute for Systems Research
Maryland Energy Innovation Institute
Dr. Rajeev Barua is a Professor of Electrical and Computer Engineering at the University of Maryland and an affiliate faculty member in the Institute for Systems Research and the Department of Computer Science. He received his Ph.D in Computer Science and Electrical Engineering from the Massachusetts Institute of Technology in 2000.
Dr. Barua is a recipient of the NSF CAREER award in 2002, and of the UMD George Corcoran Award for teaching excellence in 2003. He was a finalist for the Inventor of the Year Award in 2005 given by the Office of Technology Commercialization at the University of Maryland. He received the President of India Gold Medal for graduating from the Indian Institute of Technology in 1992 with the highest GPA in the university that year.
He served as Workshops Chair for the ACM Conference on Compilers, Architecture, & Synthesis for Embedded Systems (CASES) in 2004. He also served as Program Co-Chair for the Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES), also in 2004. Over the years, he has served on several NSF panels and on the program committees of several leading academic conferences.
Honors and awards
• NSF CAREER Award (2002)
• George Corcoran Award (2003)
• Finalist, Inventor of the Year Award, University of Maryland (3 finalists among 35 invention submissions) (2004)
Dr. Barua's research interests are in the areas of compilers, embedded systems, and computer architecture. Recent work has tackled the problem of compiler approaches to reliable software in embedded systems, memory allocation for embedded systems, and compiling to VLIW processors. Earlier work has targeted memory disambiguation technologies, instruction scheduling, ASIP customization, silicon compilation, instruction prefetching, partitioning of memory on multiprocessors, and a study of memory latency and bandwidth characteristics on multiprocessors.
Vishkin, Barua and Ghanim Introduce ICE to Eliminate Programmer’s Multi-Threading – A Productivity-Buster in Parallel Computing
Intermediate Concurrent Execution (ICE) enables tightly-synchronous threading-free programming for multi-threaded execution.TEDCO Invests $1M into Innovative Companies Including Rajeev Barua’s Startup SecondWrite LLC
SecondWrite LLC has received TEDCO funding from the state of Maryland for an amount of $100,000.Danny Kim, MWC/ARCS Lockheed Martin Scholar, will continue malware mitigation technology research
Danny receives ARCS Scholarship for third consecutive year.Matthew Gilboy wins Dean's Masters Student Research Award
Gilboy wins for his thesis, “Fighting Evasive Malware With Dvasion.”Rajeev Barua promoted to full professor
Barua is known for his work in compilers, embedded systems and computer architecture.ECE Names 2012-2013 Distinguished Dissertation Fellows
Anand, Fan, Guan, and Xie recognized for outstanding research.Alex Tzannes wins ACM Student Research Competition
Award presented for paper on improving run-time scheduling.Grad student Timothy Creech receives Space Technology Research Fellowship
Student of Rajeev Barua is one of six from the Clark School to win NASA fellowship.Intelligent Automation, Inc. to sponsor colloquia series
IAI president and ISR alumnus Vikram Manikonda announces generous support.Barua wins NSF grant for new binary rewriter
The rewriter will allow any binary code to be rewritten and improved.Barua, Cleaveland, Sussman win DARPA funding for AESOP project
UMD will collaborate with Princeton, BAE Systems to compile serial programs into parallel programs.Rajeev Barua is Principal Investigator for NSF Compiler Optimizations Grant
Uzi Vishkin is co-PI for three-year, $400,000 award.Barua, Udayakumaran awarded patent for memory allocation
Prof. Barua and his former student were awarded a patent for a new dynamic memory allocation methodology.Barua awarded NSF grant for memory management as a run-time service
Research will develop a scratch pad memory allocation strategy implemented inside a binary rewriter.ECE Professor Introduces New "Desktop Supercomputing"
Uzi Vishkin's group develops first easy-to-program parallel processing supercomputer prototype.Simulator of the Explicit Multi-Threading (XMT) Computer Architecture and Software Tools for Programming It (ISR IP)
This IP is available to license.Binary Rewriting Without Relocation Information (ISR IP)
This IP is available to license.Automatic Parallelization Using Binary Rewriting (ISR IP)
This IP is available to license.A Dynamic Memory Allocator for Embedded Systems with Scratch-Pad Memory (ISR IP)
This IP is available to license.ISR alum Haga joins faculty at National Sun Yat-Sen University, Taiwan
Former student of Rajeev Barua will continue research in compiler techniques for embedded processors.ECE Faculty Promotions Announced
Two promoted to professor and four promoted to associate professor.Shapiro, Barua, Ulukus and Wu receive tenure
Four ISR faculty promoted to associate professor rankEphremides is PI for NSF MRI grant on wireless sensor networks
Project will develop experimental prototypes of intelligent embedded systemsISR faculty win two Invention of the Year awards
Faculty recognized in information science and physical science categoriesBarua receives TEDCO "significant commercial potential" award
ISR faculty member to study “A Dynamic Memory Allocator for Embedded Systems with Scratch-Pad Memory.”Barua is co-principal investigator for five-year, $700K NSF grant
Research will investigate parallel random-access model (PRAM)-on-chip.- NSF CSR: Easy PRAM-Based High-Performance Parallel Programming with Immediate Concurrent Execution (ICE)
- Binary Rewriting without Relocation Information
- Adaptive Environment for Supercompiling with Optimized Parallelism (AESOP)
- NSF CSR-PSCE,SM: Compiler-Directed System Optimization of a Highly-Parallel Fine-Grained Chip Multiprocessor
- NSF CSR-EHS: Memory management as a run-time service